1. Field of the Invention
This invention relates to switches for programming programmable logic devices. More particularly, the present invention relates to the use of non-volatile memory devices as memory and switching elements to provide programmable bidirectional connections.
2. Art Background
Programmable logic circuits such as field programmable gate arrays (FPGA) require a large number of program controlled switching elements to connect two or more wires together in order to form the proper logic functions specified in the design. For a one time programmable device such as anti-fuse FPGAs, the connection of two or more wires are accomplished by electrically annealing a junction point (anti-fuse) with high voltage and current such that the resistance were lowered from very high to very low thus allowing conduction of signals from one wire to the other through the anti-fuse. For re-programmable FPGAs, one typical way of connecting two wires is through the use of SRAM controlled passgate as a switch. The SRAM can be programmed through standard memory programming techniques in such a way that the output of the SRAM bit can turn "on" or "off" the associated passgate thus allowing the connection of two desired wires through the passgate. However, each time the component is powered down, the states of the bits would have to be reloaded from a source, such as a non-volatile EEPROM or the like, in order to reprogram the bits.
It is readily apparent that certain distinct advantages can be achieved using non-volatile memory elements to function as the switches to program the programmable logic device. However, such prior art elements are unidirectional and incur data retention problems. FIG. 1A illustrates a prior art example of a non-volatile memory switch showing a unidirectional signal path. The two n-channel non-volatile transistors shared common gates, including the floating charge capacitor of the element. The first transistor 10 is used as a memory storage element and the second transistor 15 is used an unidirectional passgate. When the switch is turned on, a signal originating at point 20 passes through inverter 22, the second transistor 15 to level regeneration circuitry 25 which restores the signal level which was degraded through the passgate. The regenerated signal is further boosted by a second driver-inverter 30.
FIG. 1B shows another prior art example of an array of elements wherein logic 0 and logic 1 of a unidirectional switch are separately controlled to effect a unidirectional signal path to selectively produce a product term of the inputs. FIG. 1C illustrates a prior art example of using non-volatile memory to form a programmable NOR function. A non-programmable n-input NOR gate can be formed by having n parallel stages of n-channel transistor 51 with different input terminals (IT) 50 as inputs and common product terminals (PT) 52 as output with Vds (53) grounded. For programmable case, FIG. 1C shows by using transistors 54, 55 and 56 and setting the states of the common gate line (CGL) 57, word select line (WSL) 58, and WDL 59, the node Vd 53 can be programmed to be either grounded or floating. If Vd 53 is floating, then IT 50 is disconnected to be a input for the NOR structure. When Vd 53 is at ground, then IT 50 is one of the NOR inputs. By constructing an n-parallel structures of the devices of FIG. 1C with common PTs (52) and individually controlled Vds (53) to be either at ground or float, a m-input NOR function can be programmed where m is less than or equal to n. The input signals go to ITs (50) and the NOR function operates on those transistors 51 where the associated Vds (53) are grounded. The resulting output of the m-input NOR is the common product term 52.
As can be seen from the above examples, the prior art devices described are used to form programmable n-input, one output logic functions having unidirectional signal flow. In addition, other problems exist with the prior art devices. These problems will be explained with reference to FIGS. 2-5.
FIG. 2 shows a commonly known-channel non-volatile transistor in symbolic form. FIG. 3 illustrates the same n-channel non-volatile transistor in a simplified capacitor model form showing a floating charge capacitor and substrate capacitor model. It is commonly known that the voltage at node 305 (represented as X) is the fraction of the capacitance of the floating charge capacitor 310 divided by the sum of the capacitance of the floating charge capacitor 310 and the capacitance of the substrate capacitor 315 (coupling ratio) multiplied by the gate voltage. Initially, before any programming, all voltages are zero.
During erase mode, as shown in FIG. 4A, the gate is set at V++ programming voltage (Vpp) to allow electrons to flow from the source terminal to the floating gate capacitor resulting in a negative voltage on the floating gate capacitor C1. After the erase operation is complete, the source and the gate terminals are grounded, as shown in FIG. 4B, and the charged floating gate capacitor C1 is at -5 Volts. In actual circuit operation, the gate is set at Vcc which is at 5 V (or 3.3 V for low voltage operation). In the 5 V case, as shown in FIG. 4C, the node voltage 405 is at -2 Volts indicating that the transistor is at the "off" state, that is, the transistor is non-conducting.
During the programming mode, as shown in FIG. 5A, the gate terminal is coupled to ground and the source terminal is coupled to V++, the programming voltage (Vpp). In this mode, the electron charge flows from Capacitor C1 to the source terminal, resulting in a positive voltage at the floating gate capacitor. FIG. 5B shows the voltage at C1 to be 3 volts. In the normal circuit operation mode, wherein all memory cells are programmed, the gate voltage is set to Vcc, the normal power supply. In the case the voltage at C1 is at 3 volts, the voltage at node 505 is at 6 volts, which is higher than Vcc, indicating that the transistor is conducting. Since the state has a voltage higher than Vcc, the need to have the voltage level regeneration circuitry shown in FIG. 1A is eliminated. An additional feature is that the conducting resistance of the on-stage is lower as the result of the higher gate voltage thus improving the speed of the gate.
A single transistor structure as described above can be used both as non-volatile memory storage element and a switch connecting or disconnecting two lines, saving significant space on the component die. However, there are problems when using a single transistor for dual functions due to the mixing of programming lines and routing lines at the source and drain nodes of the transistor. Furthermore, when a single transistor structure is used, data retention is a problem.
Read disturbance problems arise when the passgate is conducting to couple two connectors resulting in data retention problems. A non-volatile device with stored charge on a floating gate suffers from potential charge loss over a long period of time due to undesired tunneling (charge injection) through the tunnel dielectric which consists of a thin oxide (typically less than 100 Angstroms). Such undesired tunneling is one of the primary causes of data loss. The oxide is thin to enable programming of the device. When the device is used as memory only, the data loss potential is not a problem as the duration of data read operations are brief. Typically, most manufacturers specify a minimum data retention period of ten years for devices that experience normal usage.
The undesired tunneling, however, can happen during the read operation of the memory cell when the device is in the conducting mode. A field is introduced across the dielectric due to the voltage difference between the source and the gate. For the memory cell this read period is very short hence the disturbance is minimal. For applications where the device is used for connecting two wires conducting signals from/to source to/from drain of the device, the disturbance, and therefore the tunneling across the dielectric, can be significant causing failure in the device over a short period of time.